(1) Field of the Invention
The present invention relates to a semiconductor device reducing the parasitic capacitance produced in the vicinity of a transistor and a method for fabricating the same.
(2) Description of Related Art
In recent years, as semiconductor process rules become finer, it is becoming more difficult to control the dimensions of gate electrodes constituting part of MOS transistors. In particular, the difference in the density of a gate pattern causes the difference in the influence of optical proximity effect and etching characteristics. Therefore, the dimensions of finished gate electrodes vary depending on their surrounding features. This problem will be described with reference to FIGS. 8A through 8C.
FIG. 8A is a diagram showing an example of a plan configuration of a known semiconductor device in which dummy gates are formed to reduce variations in the dimensions of finished gate electrodes, and FIGS. 8B and 8C are cross-sectional views taken along the line VIIb-VIIb and the line VIIc-VIIc in FIG. 8A, respectively.
As shown in FIGS. 8A through 8C, in the structure of the known semiconductor device, an isolation region 11 is formed in the surface of a substrate 10 to section the substrate 10 into a plurality of transistor regions. The isolation region 11 is made of, for example, a SiO2 film. A gate electrode 12 is formed on each transistor region of the substrate 10 with a gate insulating film 13 interposed therebetween. For example, N-type impurity regions 14 serving as source/drain regions are formed in each transistor region of the substrate 10 and to both sides of the gate electrode 12. To be specific, a first NMOS transistor TNa comprising a gate electrode 12a and impurity regions 14a and a second NMOS transistor TNb comprising a gate electrode 12b and impurity regions 14b are formed in the substrate 10 to be adjacent to each other with the isolation region 11 interposed between the first NMOS transistor TNa and the second NMOS transistor TNb.
The dummy gates 15 are formed on the isolation region 11 to be parallel to the gate electrodes 12. To be specific, a dummy gate 15a is formed on, out of parts of the isolation region 11 adjacent to the first NMOS transistor TNa, a part of the isolation region 11 located far from the second NMOS transistor TNb, a dummy gate 15b is formed on a part of the isolation region 11 interposed between the first NMOS transistor TNa and the second NMOS transistor TNb, and a dummy gate 15c is formed on, out of parts of the isolation region 11 adjacent to the second NMOS transistor TNb, a part of the isolation region 11 located far from the first NMOS transistor TNa.
The substrate 10, the isolation region 11, the gate electrodes 12, the gate insulating films 13, the N-type impurity regions 14, and the dummy gates 15 are covered with an interlayer insulating film 16 made of SiO2. Contact plugs 17 are formed to both sides of each gate electrode 12 to reach the N-type impurity regions 14. To be specific, contact plugs 17a and 17b are formed to reach the N-type impurity regions 14a, and contact plugs 17c and 17d are formed to reach the N-type impurity regions 14b. The contact plugs 17 each have a structure in which a contact hole is filled with a refractory metal, such as tungsten.
In the structure of such a known semiconductor device, the difference in the density of a gate pattern is reduced by locating a dummy gate 15 a predetermined distance apart from the associated gate electrode 12. This reduces variations in optical proximity effect and etching characteristics due to the density difference and reduces variations in the dimensions of finished gates.
FIG. 9 is a plan view showing an example of the structure of a known semiconductor device in which dummy gates are formed to reduce variations in the dimensions of finished gate electrodes and furthermore dummy gates that are no longer required are utilized as interconnects.
In the structure of the semiconductor device shown in FIG. 9, an isolation region (not shown) is formed in a substrate (not shown) to section the substrate into a plurality of transistor regions. A gate electrode 12c is formed on the transistor regions of the substrate with gate insulating films (not shown) interposed therebetween. For example, N-type impurity regions 14 and P-type impurity regions 18 serving as source/drain regions are formed in the corresponding transistor regions of the substrate and to both sides of the gate electrode 12c. To be specific, an NMOS transistor TNc comprising the gate electrode 12c and the N-type impurity regions 14c and a PMOS transistor TP comprising the gate electrode 12c and the P-type impurity regions 18 are formed to be adjacent to each other with the isolation region interposed between the NMOS transistor TNc and the PMOS transistor TP.
In this case, the gate electrode 12c is a single gate electrode continuously formed over both the NMOS transistor TNc and the PMOS transistor TP.
A dummy gate 15d and a dummy gate 15e are formed on both the N-type impurity regions 14c, respectively, and a dummy gate 15d and the dummy gate 15e on both the P-type impurity regions 18, respectively. Each dummy gate 15d and the dummy gate 15e are formed in parallel to the gate electrode 12c. In this case, the dummy gates 15d are separately formed on one of the N-type impurity regions 14c and one of the P-type impurity regions 18. On the other hand, the dummy gate 15e is a single dummy gate continuously formed across both the adjacent NMOS and PMOS transistors TNc and TP.
The N-type impurity regions 14c, the P-type impurity regions 18, the gate electrode 12c, and the dummy gates 15d and 15e are insulated from one another by an interlayer insulating film (not shown) made of SiO2. Contact plugs 17e and 17f are formed in the interlayer insulating film to reach the N-type impurity regions 14c of the NMOS transistor TNc and the P-type impurity regions 18 of the PMOS transistor TP. The contact plugs 17 each have a structure in which a contact hole is filled with a refractory metal such as tungsten. Furthermore, the contact plugs 17e and 17f are connected to the dummy gates 15d and 15e, respectively.
Although the dummy gates 15d and 15e are formed to reduce variations in the dimensions of the finished gate electrodes 12c, they are no longer required after the formation of the gate electrode 12c. To cope with this, the dummy gate 15e is connected to the contact plugs 17f on the associated impurity region 14c of the NMOS transistor TNc and the associated impurity region 18 of the PMOS transistor TP, thereby utilizing the dummy gate 15e as an interconnect. This can ensure a resource of an interconnect layer and improve integration density. For example, Japanese Unexamined Patent Publication No. 2002-208643 (page 10, FIG. 5) discloses the above-mentioned technique.